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description the M37735S4BFP is a microcomputer using the 7700 family core. this microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. this microcomputer also includes a 32 khz oscillation circuit, in addition to the ram, multiple-function timers, serial i/o, a-d converter, and so on. features l number of basic instructions .................................................. 103 l memory size ram ................................................ 2048 bytes l instruction execution time the fastest instruction at 25 mhz frequency ...................... 160 ns l single power supply ...................................................... 5 v 10% l low power dissipation (at 25 mhz frequency) ............................................ 47.5 mw (typ.) l interrupts ............................................................ 19 types, 7 levels l multiple-function 16-bit timer ................................................. 5 + 3 l serial i/o (uart or clock synchronous)..........................................3 l 10-bit a-d converter ..............................................8-channel inputs l 12-bit watchdog timer l programmable input/output (ports p4, p5, p6, p7, p8) ..............................................................37 l clock generating circuit ........................................ 2 circuits built-in application control devices for general commercial equipment such as office automation, office equipment, and so on. control devices for general industrial equipment such as communication equipment, and so on. pin configuration (top view) preliminary notice: this is not a final specification. some parametric limits are subject to change. hold p2 7 /a 7 /d 7 25 27 26 28 34 29 31 32 33 35 38 39 40 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /i nt 2 p6 3 /i nt 1 p6 2 /i nt 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in / ki 3 /rtp1 3 p5 6 /ta3 out / ki 2 /rtp1 2 p5 5 /ta2 in / ki 1 /rtp1 1 p5 4 /ta2 out / ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 1 4 3 2 5 p8 4 / cts 1 / rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 / cs 0 p0 1 / cs 1 p0 2 / cs 2 p0 3 / cs 3 p0 4 / cs 4 p0 5 / rsmp p0 6 /a 16 p0 7 /a 17 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 67 66 65 70 outline 80p6n-a p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 0 /d 0 p2 1 /a 1 /d 1 p2 2 /a 2 /d 2 p2 3 /a 3 /d 3 43 42 41 M37735S4BFP 22 23 24 rdy p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p7 4 /an 4 /r x d 2 p7 3 /an 3 /clk 2 p7 2 /an 2 / cts 2 p7 1 /an 1 p7 5 /an 5 / ad trg /t x d 2 p7 6 /an 6 /xc out p7 7 /an 7 /xc in v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 / clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 reset x out p3 2 / ale p3 0 / wel p3 1 / weh cnv ss v ss byte x in p2 6 /a 6 /d 6 p2 5 /a 5 /d 5 p2 4 /a 4 /d 4 rde p3 3 / hlda 37 36 30 68 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer
2 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. M37735S4BFP block diagram x in x out reset reset input v ref p8(8) p7(8) p5(8) p6(8) p4(5) address (18)/data (16) cnvss byte uart1(9) uart0(9) av ss (0v) av cc (0v) v ss v cc a-d converter(10) x cin x cout x cin x cout clock input clock output reference voltage input external data bus width selection input clock generating circuit instruction register(8) arithmetic logic unit(16) accumulator a(16) accumulatcr b(16) index register x(16) index register y(16) stack pointer s(16) direct page register dpr(16) input butter register ib(16) data bank register dt(8) program bank register pg(8) incrementer/decrementer(24) data address register da(24) incrementer(24) instruction queue buffer q 2 (8) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer db l (8) data buffer db h (8) ram 2048 bytes timer ta3(16) timer ta4(16) timer ta2(16) timer ta1(16) timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) address bus data bus(odd) data bus(even) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p4 address bus/data bus uart2(9 ) wel weh ale hlda hold rdy 1 rde rsmp cs 0 cs 1 cs 2 cs 3 cs 4 processor status register ps(11) program counter pc(16) program address register pa(24)
3 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. parameter functions number of basic instructions 103 instruction execution time 160ns (the fastest instruction at external clock 25 mhz frequency) memory size ram 2048 bytes p5 C p8 8-bit 5 4 p4 5-bit 5 1 ta0, ta1, ta2, ta3, ta4 16-bit 5 5 tb0, tb1, tb2 16-bit 5 3 serial i/o (uart or clock synchronous serial i/o) 5 3 a-d converter 10-bit 5 1 (8 channels) watchdog timer 12-bit 5 1 3 external types, 16 internal types each interrupt can be set to the priority level (0 C 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) supply voltage 5 v 10% 47.5 mw (at external clock 25 mhz frequency) input/output voltage 5 v output current 5 ma memory expansion maximum 1 mbytes operating temperature range C20 to 85 c device structure cmos high-performance silicon gate process package 80-pin plastic molded qfp (80p6n-a) functions of M37735S4BFP input/output ports multi-function timers interrupts clock generating circuit power dissipation input/output characteristic
4 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. pin description pin name input/output functions vcc, power source apply 5 v 10% to vcc and 0 v to vss. vss cnvss cnvss input input connect to vcc. _____ reset reset input input when l level is applied to this pin, the microcomputer enters the reset state. these are pins of main-clock generating circuit. connect a ceramic resonator or a quartz-crystal oscillator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. ____ rde read enable output output ____ when data/instruction read is performed, output level of rde signal is l. byte bus width input this pin determines whether the external data bus has an 8-bit width or a 16-bit width. selection input the data bus has a 16-bit width when l signal is input and an 8-bit width when h signal is input. avcc, analog power power source input pin for the a-d converter. externally connect avcc to vcc and avss to vss. avss source input v ref reference input this is reference voltage input pin for the a-d converter. voltage input ____ p0 0 / cs 0 C chip selection output ____ ____ when the specified external memory area is accessed, cs 0 C cs 4 signals are l. ____ p0 4 / cs 4 output _____ p0 5 / rsmp ready sampling output ____ the timing signal to be input to the rdy pin is output. output p0 6 /a 16 , address output output an address (a 16 , a 17 ) is output. p0 7 /a 17 p1 0 /a 8 /d 8 C address output i/o when the byte pin is set to l and external data bus has a 16-bit width, high-order data p1 7 /a 15 /d 15 /data (high (d 8 C d 15 ) is input/output or an address (a 8 C a 15 ) is output. when the byte pin is h and an -order) i/o external data bus has an 8-bit width, only address (a 8 C a 15 ) is output. p2 0 /a 0 /d 0 C address output i/o low-order data (d 0 C d 7 ) is input/output or an address (a 0 C a 7 ) is output. p2 7 /a 7 /d 7 /data (low -order) i/o ____ p3 0 / wel write enable output ____ when the byte pin is l and writing to an even address is performed, output level of wel signal output is l. when the byte pin is h and writing to an even address or an odd address is performed, ____ output level of wel signal is l. ____ p3 1 / weh write enable output ____ when the byte pin is l and writing to an odd address is performed, output level of weh signal high output ____ is l. when the byte pin is h, weh signal is always h. p3 2 /ale address latch output this is used to retrieve only the address from the multiplex signal which consists of address and enable output data. _____ p3 3 / hlda hold acknow- output this outputs l level when the microcomputer enters hold state after a hold request is accepted. ledge output _____ hold hold request input _____ this is an input pin for hold request signal. the microcomputer enters hold state while this input signal is l. ____ rdy ready input input ____ this is an input pin for rdy signal. the microcomputer enters ready state while this signal is l. p4 2 / 1 clock output output this pin outputs the clock 1 . p4 3 C p4 7 i/o port p4 i/o these pins become a 5-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these ports are in the input mode when reset. p5 0 C p5 7 i/o port p5 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for timers ___ ___ a0 to a3 and input pins for key input interrupt input ( ki 0 C ki 3 ). p6 0 C p6 7 i/o port p6 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for timer ____ ____ a4, input pins for external interrupt input ( int 0 C int 2 ) and input pins for timers b0 to b2. p6 7 also functions as sub-clock sub output pin. p7 0 C p7 7 i/o port p7 i/o in addition to having the same functions as port p4, these pins function as input pins for a-d converter. p7 2 to p7 5 also function as i/o pins for uart2. additionally, p7 6 and p7 7 have the function as the output pin (x cout ) and the input pin (x cin ) of the sub-clock (32 khz) oscillation circuit, respectively. when p7 6 and p7 7 are used as the x cout and x cin pins, connect a resonator or an oscillator between the both. p8 0 C p8 7 i/o port p8 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for uart 0 and uart 1. x in clock input input x out clock output output
5 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. basic function blocks the M37735S4BFP has the same functions as the m37735mhbxxxfp except for the following: (1) the memory map is different. (2) the processor mode is different. (3) the reset circuit is different. (4) pulse output port mode of timer a is available. (5) the function of rom area modification is not available. refer to the section on the m37735mhbxxxfp, except for above (1)C(5). memory the memory map is shown in figure 1. the address space has a capacity of 16 mbytes and is allocated to addresses from 0 16 to ffffff 16 . the address space is divided by 64-kbyte unit called bank. the banks are numbered from 0 16 to ff 16 . however, banks 10 16 Cff 16 of the M37735S4BFP cannot be accessed. built-in ram and control registers for internal peripheral devices are assigned to bank 0 16 . addresses ffd6 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. use rom for memory of this address. the 2048-byte area allocated to addresses from 80 16 to 87f 16 is the built-in ram. in addition to storing data, the ram is used as stack during a subroutine call or interrupts. peripheral devices such as i/o ports, a-d converter, serial i/o, timer, and interrupt control registers are allocated to addresses from 0 16 to 7f 16 . a 256-byte direct page area can be allocated anywhere in bank 0 16 by using the direct page register (dpr). in the direct page addressing mode, the memory in the direct page area can be accessed with two words. hence program steps can be reduced. fig. 1 memory map a-d/uart2 trans./rece. timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 0 watchdog timer dbc brk instruction zero divide reset internal peripheral devices control registers refer to fig. 2 for detail information interrupt vector table 000000 16 00ffff 16 010000 16 01ffff 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ff0000 16 ffffff 16 bank ff 16 bank fe 16 00ffff 16 00ffd6 16 00087f 16 000000 16 00007f 16 000080 16 internal ram 2048 bytes 00fffe 16 00ffd6 16 00007f 16 000000 16 uart1 transmission uart1 receive uart0 transmission uart0 receive ??????????????????? int 1 : internal : external note. banks 10 16 ?f 16 cannot be accessed in the M37735S4BFP.
6 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 2 location of internal peripheral devices and interrupt control registers uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register a-d register 0 a-d register 2 port p1 register port p0 direction register port p2 register port p3 register port p4 register port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register pulse output data register 1 pulse output data register 0 a-d register 6 a-d register 7 waveform output mode register uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register reserved area (note) note. writing to reserved area is disabled.
7 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. pulse output port mode the pulse motor drive waveform can be output by using plural internal timer a. figure 3 shows a block diagram for pulse output port mode. in the pulse output port mode, two pairs of four-bit pulse output ports are used. whether using pulse output port or not can be selected by waveform output selection bit (bit 0, bit 1) of waveform output mode register (62 16 address) shown in figure 4. when bit 0 of waveform output selection bit is set to 1, rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 are used as pulse output ports, and when bit 1 of waveform output selection bit is set to 1, rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 are used as pulse output ports. when bits 1 and 0 of waveform output selection bit are set to1, rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 , and rtp0 0 , rtp0 1 , rtp0 2, and rtp0 3 are used as pulse output ports. the ports not used as pulse output ports can be used as normal parallel ports, timer input/output or key input interruput input. in the pulse output port mode, set timers a0 and a2 to timer mode as timers a0 and a2 are used. figure 5 shows the bit configuration of timer a0, a2 mode registers in pulse output port mode. data can be set in each bit of the pulse output data register corresponding to four ports selected as pulse output ports. figure 6 shows the bit configuration of the pulse output data register. the contents of the pulse output data register 1 (low-order four bits of 1c 16 address) corresponding to rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 is output to the ports each time the counter of timer a2 becomes 0000 16 . the contents of the pulse output data register 0 (low-order four bits of 1d 16 address) corresponding to rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 is output to the ports each time the counter of timer a0 becomes 0000 16 . figure 7 shows example of waveforms in pulse output port mode. when 0 is written to a specified bit of the pulse output data register,l level is output to the corresponding pulse output port when the counter of corresponding timer becomes 0000 16 , and when 1 is written, h level is output to the pulse output port. pulse width modulation can be applied to each pulse output port. since pulse width modulation involves the use of timers a1 and a3, activate these timers in pulse width modulation mode. fig. 3 block diagram for pulse output port mode timer a2 pulse width modulation output by timer a3 pulse width modulation output by timer a1 d 3 d 2 d 1 d 0 d d d d q q q q t d 11 d 10 d 9 d 8 d d d d q q q q t timer a0 pulse output data register 0 (1d 16 address) pulse output data register 1 (1c 16 address) pulse width modulation selection bit (bit 4, 5 of 62 16 address) rtp1 3 (p5 7 ) rtp1 2 (p5 6 ) rtp1 1 (p5 5 ) rtp1 0 (p5 4 ) rtp0 3 (p5 3 ) rtp0 2 (p5 2 ) rtp0 1 (p5 1 ) rtp0 0 (p5 0 ) polarity selection bit (bit 3 of 62 16 address) 45 data bus (odd) data bus (even)
8 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 are applied pulse width modulation by timer a3 by setting the pulse width modulation selection bit by timer a3 (bit 5) of the waveform output mode register to 1. rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 are applied pulse width modulation by timer a1 by setting the pulse width modulation selection bit by timer a1 (bit 4) of the waveform output mode register to 1. the contents of the pulse output data register 0 can be reversed and output to pulse output ports rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 by the polarity selection bit (bit 3) of the waveform output mode register. when the polarity selection bit is 0, the contents of the pulse output data register 0 is output unchangeably, and when 1, the contents of the pulse output data register 0 is reversed and output. when pulse width modulation is applied, likewise the polarity reverse to pulse width modulation can be selected by the polarity selection bit. fig. 4 waveform output mode register bit configuration fig. 5 timer a0, a2 mode register bit configuration in pulse output port mode fig. 6 pulse output data register bit configuration weveform output selection bit 0 0 : parallel port 0 1 : rtp1 selected 1 0 : rtp0 selected 1 1 : rtp1 and rtp0 selected pulse width modulation selection bit by timer a3 0 : not modulated 1 : modulated always ? 765432 0 1 weveform output mode register 62 16 address polarity selection bit 0 : positive polarity 1 : negative polarity pulse width modulation selection bit by timer a1 0 : not modulated 1 : modulated 0 always ?00?in pulse output port mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 765432 0 1 timer a0 mode register 56 16 timer a2 mode register 58 16 address not used in pulse output port mode always ?0?in pulse output port mode 0 0 x 1 0 0 rtp1 0 output data 765432 0 1 pulse output data register 1 1c 16 address rtp1 1 output data rtp1 2 output data rtp1 3 output data rtp0 0 output data 765432 0 1 address rtp0 1 output data rtp0 2 output data rtp0 3 output data pulse output data register 0 1d 16
9 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 7 example of waveforms in pulse output port mode output signal at each time when timer a2 becomes 0000 16 example of pulse output port (rtp1 0 ?rtp1 3 ) rtp1 3 (p5 7 ) rtp1 1 (p5 5 ) rtp1 0 (p5 4 ) rtp1 2 (p5 6 ) output signal at each time when timer a2 becomes 0000 16 example of pulse output port (rtp1 0 ?rtp1 3 ) when pulse width modulation is applied by timer a3. rtp1 3 (p5 7 ) rtp1 1 (p5 5 ) rtp1 0 (p5 4 ) rtp1 2 (p5 6 ) output signal at each time when timer a0 becomes 0000 16 example of pulse output port (rtp0 0 ?rtp0 3 ) when pulse width modulation is applied by timer a1 with polarity selection bit = ?? rtp0 3 (p5 3 ) rtp0 1 (p5 1 ) rtp0 0 (p5 0 ) rtp0 2 (p5 2 )
10 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. processor mode only the microprocessor mode can be selected. ___ figure 9 shows the functions of pins p0 0 / cs 0 p4 7 in the microprocessor mode. figure 10 shows external memory area for the microprocessor mode. access to the external memory is affected by the byte pin, the wait bit (bit 2 of the processor mode register 0 at address 5e 16 ), and the wait selection bit (bit 0 of the processor mode register 1 at address 5f 16 ) . ? byte pin when accessing the external memory, the level of the byte pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. the data bus has a width of 8 bits when level of the byte pin is h, and pins p2 0 /a 0 /d 0 p2 7 /a 7 /d 7 are the data i/o pins. the data bus has a width of 16 bits when the level of the byte pin is l, and pins p2 0 /a 0 /d 0 p2 7 /a 7 /d 7 and pins p1 0 /a 8 /d 8 p1 7 /a 15 / d 15 are the data i/o pins. when accessing the internal memory, the data bus always has a width of 16 bits regardless of the byte pin level. not used must be 10 (10 after reset) wait bit 0 : wait 1 : no wait software reset bit reset occurs when this bit is set to 1 interrupt priority detection time selection bit 0 0 : internal clock 5 7 (cycle) 0 1 : internal clock 5 4 (cycle) 1 0 : internal clock 5 2 (cycle) must be 0 765432 0 1 0 processor mode register 0 address 5e 16 address 5f 16 processor mode register 1 wait selection bit 0 : wait 0 1 : wait 1 765432 0 1 10 fig. 8 processor mode register bit configuration
11 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. ___ fig. 9 functions of pins p0 0 / cs 0 to p4 7 in microprocessor mode note. the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the 1 output in the microprocessor ___ ___ ___ mode. in this mode, signals rde , wel , weh can also be fixed to h when the internal memory area is accessed. p3 0 / wel p3 1 / weh p3 2 / ale p3 3 / hlda (note) ale weh wel hlda (note) p3 0 / wel, p3 1 / weh , p3 2 /ale, p3 3 / hlda hold rdy p4 2 / 1 p0 0 / cs 0 to p0 4 / cs 4 address data(odd) address a 8 C a 15 address data(even) address data (odd,even) i/o port pm 1 pm 0 mode 1 0 microprocessor mode (note) pin rde cs 0 to cs 4 rsmp , a 16 , a 17 p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 byte = l byte = h byte = l byte = h hold , rdy , p4 2 / 1 , ports p4 3 to p4 7 rde p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 rsmp cs 0 cs 4 rdy hold p0 5 / rsmp p2 0 /a 0 /d 0 to p2 7 /a 7 /d 7 a 8 to a 15 p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 p2 0 /a 0 /d 0 to p2 7 /a 7 /d 7 a 0 to a 7 p2 0 /a 0 /d 0 to p2 7 /a 7 /d 7 a 0 to a 7 rde, wel, weh rde, wel, weh rde, wel, weh rde, wel, weh rde, wel, weh rde, wel, weh (note) address a 16 , a 17 p0 6 /a 16 p0 7 /a 17 p4 3 to p4 7
mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 11 relationship between wait bit, wait selection bit, and access time ? wait bit as shown in figure 11, when the external memory area is accessed with the wait bit (bit 2 of the processor mode register 0 at address 5e 16 ) cleared to 0, the access time can be extended compared with no wait (the wait bit is 1). the access time is extended in two ways and this is selected with the wait selection bit (bit 0 of the processor mode register 1 at address 5f 16 ). when this bit is 1, the access time is 1.5 times compared to that for no wait. when this bit is 0, the access time is twice compared to that for no wait. at reset, the wait bit and the wait selection bit are 0. access to internal memory area is always performed in the no wait mode regardless of the wait bit. the processor modes are described below. fig. 10 external memory area for microprocessor mode (1) microprocessor mode [10] the microcomputer enters the microprocessor mode after connecting the cnvss pin to vcc and starting from reset. ___ ___ pin rde is the output pin for the read enable signal (rde) . ___ rde is l during the data read term in the read cycle. when the ___ internal memory area is read, rde can be fixed to h by setting the signal output disabe selection bit (bit 6 of the oscillation circuit control register 0) to 1. sfr ram microprocessor mode the shaded area is the external memory area. note that banks 10 16 to ff 16 cannot be accessed. 00 16 80 16 87f 16 internal clock a i /d i rde or wel , weh ale wait bit 1 (no wait) a i /d i rde or wel , weh ale wait bit 0 (wait 1) access time access time address data address data address data address data a i /d i rde or wel , weh ale wait bit 0 (wait 0) access time address data address 12
13 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. ___ ___ cs 0 to cs 4 are the chip select signals and are l when the address ____ shown in table 2 is accessed. rsmp is the ready-sampling signal ___ which is output for the rdy input described later when the external ____ memory area is accessed. by inputting logical and of rsmp and ___ ____ cs n (n = 0 to 4) to the rdy pin, read/write term for any address areas can be extended by 1 cycle of clock 1 . in addition, the read/write term can also be extended by 2 cycles of clock 1 if the above function and wait 0/1 function specified with the wait bit are used together. pins p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 have two functions depending on the level of the byte pin. when the byte pin level is l, pins p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 function ___ ___ ___ as address (a 8 to a 15 ) output pins while rde or wel , weh are h and as odd address data i/o pins while these signals are l. however, ___ if an internal memory is read, external data is ignored while rde is l. when the byte pin level is h, pins p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 function as address (a 8 to a 15 ) output pins. pins p2 0 /a 0 /d 0 p2 7 /a 7 /d 7 have two functions depending on the level of the byte pin. when the byte pin level is l, pins p2 0 /a 0 /d 0 p2 7 /a 7 /d 7 function ___ ___ ___ as address (a 0 to a 7 ) output pins while rde or wel , weh are h and as even address data i/o pins while these signals are l. however, ___ if an internal memory is read, external data is ignored while rde is l. when the byte pin level is h, pins p2 0 /a 0 /d 0 p2 7 /a 7 /d 7 function ___ ___ ___ as address (a 0 to a 7 ) output pins while rde or wel , weh are h and as even and odd address data i/o pins while these signals are l. however, if an internal memory is read, external data is ignored while ___ rde is l. ___ ___ wel , weh are the write-enable low signal and the write-enable high signal, respectively. these signals are l during the data write term of the write cycle, but their operations differ depending on the byte pin level. ___ in the case the byte pin level is l, wel is l when writing to ___ an even address, weh is l when writing to an odd address, and ___ ___ both wel and weh are l when writing to even and odd addresses. in the case the byte pin level is h, regardless of address, only ___ ___ ___ ___ wel is l, and weh retains h. wel and weh can also be fixed to ___ h when the internal memory is accessed, same as rde , by writing 1 to the signal output disable selection bit. ale is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. the latch is transparent while ale is h to let the address signal pass through and held while ale is l. ____ hlda is a hold acknowledge signal and is used to notify externally ____ when the microcomputer receives hold input and enters into hold state. ____ hold is a hold request signal. it is an input signal used to put the ____ microcomputer in hold state. hold input is accepted when the internal clock falls from h level to l level while the bus is not used. ___ ____ ___ pins p0 0 / cs 0 p3 1 / weh and rde are floating while the microcomputer ____ stays in hold state. after hlda signal changes to l level and one cycle of internal clock passed, these ports become floating. after ____ hlda signal changes to h level and one cycle of internal clock passed, these ports are released from floating state. ___ rdy is a ready signal. if this signal goes l, the internal clock ___ stops at l. rdy is used when slow external memory is attached. p4 2 / 1 pin is an output pin for clock 1 . the 1 output is ___ independent of rdy and does not stop even when internal clock ___ stops because of l input to the rdy pin.
mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. as shown in table 3, 1 output can be stopped with the signal output disable selection bit = 1. in this case, write 1 to the port p4 2 direction register. table 1 shows the relationship between the cnvss pin input level and the processor mode. table 1. relationship between cnvss pin input levels and processor mode cnvss mode description microprocessor mode upon starting after reset. ? microprocessor vcc 00 0880 16 to 00 7fff 16 00 8000 16 to 03 ffff 16 04 0000 16 to 07 ffff 16 08 0000 16 to 0b ffff 16 0c 0000 16 to 0f ffff 16 table 2. relationship between access addresses and chip-select signals cs 0 to cs 4 access address microprocessor mode chip-select signal area the latter half of bank 00 16 except internal memory area and banks 01 16 to 03 16. banks 04 16 to 07 16 banks 08 16 to 0b 16 banks 0c 16 to 0f 16 the first half of bank 00 16 except internal memory area ____ cs 0 ____ cs 1 ____ cs 2 ____ cs 3 ____ cs 4 table 3. function of signal output disable selection bit cm 6 (bit 6 of oscillation circuit control register 0) function cm 6 = 0 cm 6 = 1 processor mode pin note. functions shown in table 3 cannot be emulated with a debugger. for the oscillation circuit control register 0 and port function control register, refer to figures 64 and 11 in data sheet m37735mhbxxxfp, respectively. ___ ___ ___ rde , wel , weh are output when the internal/external memory area is accessed. after wit/stp instruction is executed, h is output. clock 1 is output independent of 1 output selection bit. ___ ___ ___ rde , wel , weh are output only when the external memory area is accessed. l is output after wit/stp instruction is executed * standby state selection bit (bit 0 of port function control register) must be set to 1. h or l is output. (contents of p4 2 port latch is output.) * port p4 2 direction register must be set to 1. ___ rde , ___ wel , weh ___ rde 1 microprocessor mode 14
15 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. reset circuit _____ the microcomputer is released from the reset state when the reset pin is returned to h level after holding it at l level with the power source voltage at 5 v 10%. program execution starts at the address formed by setting address a 23 C a 16 to 00 16 , a 15 C a 8 to the contents of address ffff 16 , and a 7 C a 0 to the contents of address fffe 16 . figure 13 shows an example of a reset circuit. if the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 v or less when the power source voltage reaches 4.5 v. if a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from l to h after the main-clock oscillation is fully stabilized. figure 12 shows the status of the internal registers during reset. fig. 12 microcomputer internal status during reset 00 16 address 00 16 0000 00 16 00 16 00 16 00 16 00 16 00 16 0 11 00 00 0 0 ??? 00 16 00 16 0 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10 00 16 000 0 0 00 16 00 16 00 16 00 16 00 16 00 16 0 001 00 0 0 001 001 00 0 0 00 0 0 0 00 16 (04 16 ) ??? (05 16 ) ??? (08 16 ) ??? (09 16 ) ??? (0c 16 ) ??? (0d 16 ) ??? (10 16 ) ??? (11 16 ) ??? (14 16 ) ??? (1e 16 ) ??? (1f 16 ) ??? (30 16 ) ??? (38 16 ) ??? (34 16 ) ??? (3c 16 ) ??? (35 16 ) ??? (3d 16 ) ??? (40 16 ) ??? (42 16 ) ??? (44 16 ) ??? (56 16 ) ??? (57 16 ) ??? (58 16 ) ??? (59 16 ) ??? (5a 16 ) ??? (5b 16 ) ??? (5c 16 ) ??? (5d 16 ) ??? (5e 16 ) ??? (5f 16 ) ??? port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register a-d control register 0 a-d control register 1 uart 0 transmit/receive mode register uart 1 transmit/receive control register 1 uart 1 transmit/receive mode register uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 uart 0 transmit/receive control register 1 count start flag one- shot start flag up-down flag timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 address (60 16 ) ??? (7f 16 ) ??? (61 16 ) ??? (6c 16 ) ??? (6d 16 ) ??? (6e 16 ) ??? (6f 16 ) ??? (70 16 ) ??? (71 16 ) ??? (72 16 ) ??? (73 16 ) ??? (74 16 ) ??? (75 16 ) ??? (76 16 ) ??? (77 16 ) ??? (78 16 ) ??? (79 16 ) ??? (7a 16 ) ??? (7b 16 ) ??? (7c 16 ) ??? (7d 16 ) ??? (7e 16 ) ??? watchdog timer register watchdog timer frequency selection flag oscillation circuit control register 0 port function control register serial transmit control register oscillation circuit control register 1 a-d/uart2 trans./rece. interrupt control register uart 0 transmission interrupt control register uart 0 receive interruupt control register uart 1 transmission interrupt control register uart 1 receive interruupt control register timer a0 interrupt control register timer b2 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register processor status register (ps) program bank register (pg) program counter (pc h ) program counter (pc l ) direct page register (dpr) data bank register (dt) int 0 interrupt control register int 1 interrupt control register int 2 /key input interrupt control register 0 contents of other registers and ram are undefined during reset. initialize them by software. ? 0 0 0 0000 ? 0 000 000 000 0 00 1?? 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 00 0 0 0 00 16 content of ffff 16 content of fffe 16 0000 16 fff 16 0 0 0 0 0 0 00 16 00 16 (62 16 ) ??? (64 16 ) ??? (68 16 ) ??? waveform output mode register uart2 transmit/receive mode register uart2 transmit/receive control register 0 0 0 (69 16 ) ??? uart2 transmit/receive control register 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 000 1 0 0 0 0 0 0 0 0 0 0 0
mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. v cc reset reset v cc 0 v 0 v 4.5 v 0.9 v power on note. in this case, stabilized clock is input from the external to the main-clock oscillation circuit. perform careful evaluation at the system design level before using. addressing modes the M37735S4BFP has 28 powerful addressing modes.refer to the mitsubishi semiconductors data book single-chip 16- bit microcomputers for the details of each addressing mode. machine instruction list the M37735S4BFP has 103 machine instructions. refer to the mitsubishi semiconductors data book single-chip 16- bit microcomputers for details. fig. 13 example of a reset circuit 16
17 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. symbol parameter conditions ratings unit vcc power source voltage C0.3 to +7 v avcc analog power source voltage C0.3 to +7 v v i _____ input voltage reset , cnvss, byte C0.3 to +12 v input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ ____ p8 0 C p8 7 , v ref , x in , hold , rdy output voltage ___ p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ____ _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda ,p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , ____ x out , rde p d power dissipation ta = 25 c 300 mw t opr operating temperature C20 to +85 c t stg storage temperature C40 to +150 c absolute maximum ratings v i v o C0.3 to vcc + 0.3 v C0.3 to vcc + 0.3 v limits min. typ. max. f(x in ) : operating 4.5 5.0 5.5 f(x in ) : stopped, f(x cin ) = 32.768 khz 2.7 5.5 avcc analog power source voltage vcc v vss power source voltage 0v avss analog power source voltage 0 v high-level input voltage ____ ___ hold , rdy , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , x in , reset , cnvss, byte, x cin (note 3) high-level input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 ____ ___ low-level input voltage hold , rdy , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , x in , reset , cnvss, byte, x cin (note 3) low-level input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 ___ high-level peak output current p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ____ _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 ___ high-level average output current p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ____ _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 ___ low-level peak output current p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ____ _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level peak output current p4 4 C p4 7 , p5 0 C p5 3 ___ low-level average output current p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ____ _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 ,p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 i ol(avg) low-level average output current p4 4 C p4 7 , p5 0 C p5 3 15 ma f(x in ) main-clock oscillation frequency (note 4) 25 mhz f(x cin) sub-clock oscillation frequency 32.768 50 khz unit recommended operating conditions (vcc = 5 v 10%, ta = C20 to +85 c, unless otherwise noted) notes 1. average output current is the average value of a 100 ms interval. ___ ____ _____ 2. the sum of i ol(peak) for ports p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / hlda and p8 must ___ ____ be 80 ma or less, the sum of i oh(peak) for ports p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 0 / wel C p3 3 / _____ hlda and p8 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, and p7 must be 100 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3. limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4. the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1. 0.8 vcc 0.5 vcc 0 0 v v v v ma ma ma ma ma parameter symbol vcc power source voltage vcc vcc 0.2vcc 0.16vcc v C10 C5 10 20 5 v ih v ih v il v il i oh(peak) i oh(avg) i ol(peak) i ol(peak) i ol(avg)
18 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. unit electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions 4.7 v v v oh v oh v oh v ol 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.1 v oh v ol v ol v ol v ol v t+ C v tC v t+ C v tC v t+ C v tC v t+ C v tC i ih i il 2 3 v v v 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.4 0.4 5 v v v v v v v v a a a C5 C5 C0.5 C1.0 ma v i il limits min. typ. max. v ram C0.25 2 ___ high-level output voltage p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 ___ high-level output voltage p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 3 / hlda , p4 2 / 1 ____ ____ high-level output voltage p3 0 / wel , p3 1 / weh , p3 2 /ale ____ high-level output voltage rde ___ low-level output voltage p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level output voltage p4 4 C p4 7 , p5 0 C p5 3 ___ low-level output voltage p0 0 / cs 0 C p0 7 /a 17 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _____ p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p3 3 / hlda , p4 2 / 1 ____ ____ low-level output voltage p3 0 / wel , p3 1 / weh , p3 2 /ale ____ low-level output voltage rde ____ ___ hysteresis hold , rdy , ta0 in C ta4 in , tb0 in C tb2 in , ____ ____ _____ ____ ____ ____ int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , ___ ___ clk 1 , clk 2 , ki 0 C ki 3 _____ hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , x in , reset , cnvss, byte low-level input current p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 0 /d 0 C p2 7 /a 7 /d 7 , p4 3 C p4 7 , p5 0 C p5 3 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , x in , reset , cnvss, byte low-level input current p5 4 C p5 7 , p6 2 C p6 4 ram hold voltage i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i ol = 10 ma i ol = 20 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped.
19 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ): stopped in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when a wit instruction is executed (note 2) v cc = 5 v, f(x in ) : stopped, f(x cin ) = 32.768 khz, in operating (note 3) v cc = 5 v, f(x in ) : stopped, f(x cin ) = 32.768 khz, when a wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped ma ma a a a a a max. 22.8 3.2 20 120 10 1 20 limits typ. 11.4 1.6 10 60 5 unit min. test conditions symbol parameter electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to +85 c, unless otherwise noted) notes 1. this applies when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output stop bit = 1. 2. this applies when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3. this applies when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4. this applies when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. limits min. typ. max. resolution v ref = v cc 10 bits absolute accuracy v ref = v cc 3 lsb r ladder ladder resistance v ref = v cc 10 25 k w t conv conversion time 9.44 s v ref reference voltage 2 v cc v v ia analog input voltage 0 v ref v symbol parameter test conditions unit aCd converter characteristics (v cc = av cc = 5 v, v ss = av ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. i cc power source current when external bus is in use, output pins are open, and other pins are v ss .
20 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. limits min. max. t c external clock input cycle time (note 1) 40 ns t w(h) external clock input high-level pulse width (note 2) 15 ns t w(l) external clock input low-level pulse width (note 2) 15 ns t r external clock rise time 8ns t f external clock fall time 8ns limits min. max. t su(dCrde) data input setup time 32 ns t su(rdyC 1) ___ rdy input setup time 55 ns t su(holdC 1) ____ hold input setup time 55 ns t h(rdeCd) data input hold time 0ns t h( 1Crdy) ___ rdy input hold time 0ns t h( 1Chold) ____ hold input hold time 0ns timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note 1)) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mh z . 2. input signals rise/fall time must be 100 ns or less, unless otherwise noted. external clock input unit symbol parameter notes 1. when the main clock division selection bit = 1, the minimum value of t c = 80 ns. 2. when the main clock division selection bit = 1, values of t w(h) / t c and t w(l) / t c must be set to values from 0.45 through 0.55. unit symbol parameter microprocessor mode microprocessor mode unit symbol parameter limits min. max. t su(p4dCrde) port p4 input setup time 60 ns t su(p5dCrde) port p5 input setup time 60 ns t su(p6dCrde) port p6 input setup time 60 ns t su(p7dCrde) port p7 input setup time 60 ns t su(p8dCrde) port p8 input setup time 60 ns t h(rdeCp4d) port p4 input hold time 0ns t h(rdeCp5d) port p5 input hold time 0ns t h(rdeCp6d) port p6 input hold time 0ns t h(rdeCp7d) port p7 input hold time 0ns t h(rdeCp8d) port p8 input hold time 0ns
21 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. limits min. max. t c(ta) tai in input cycle time 80 ns t w(tah) tai in input high-level pulse width 40 ns t w(tal) tai in input low-level pulse width 40 ns unit symbol parameter timer a input (count input in event counter mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width (note) 160 ns t w(tal) tai in input low-level pulse width (note) 160 ns unit symbol parameter timer a input (gating input in timer mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in one-shot pulse mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in pulse width modulation mode) limits min. max. t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high-level pulse width 1000 ns t w(upl) tai out input low-level pulse width 1000 ns t su(upCt in ) tai out input setup time 400 ns t h(t in Cup) tai out input hold time 400 ns unit symbol parameter timer a input (up-down input in event counter mode) unit timer a input (two-phase pulse input in event counter mode) limits min. max. t c(ta) taj in input cycle time 800 ns t su(taj in Ctaj out ) taj in input setup time 200 ns t su(taj out Ctaj in ) taj out input setup time 200 ns symbol parameter
22 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. limits min. max. t c(tb) tbi in input cycle time (one edge count) 80 ns t w(tbh) tbi in input high-level pulse width (one edge count) 40 ns t w(tbl) tbi in input low-level pulse width (one edge count) 40 ns t c(tb) tbi in input cycle time (both edges count) 160 ns t w(tbh) tbi in input high-level pulse width (both edges count) 80 ns t w(tbl) tbi in input low-level pulse width (both edges count) 80 ns unit symbol parameter timer b input (count input in event counter mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse period measurement mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns unit symbol parameter a-d trigger input unit symbol parameter serial i/o unit symbol parameter ____ ___ external interrupt int i input, key input interrupt ki i input limits min. max. t w(inh) ____ int i input high-level pulse width 250 ns t w(inl) ____ int i input low-level pulse width 250 ns t w(kil) ___ ki i input low-level pulse width 250 ns limits min. max. t c(ad) _____ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) _____ ad trg input low-level pulse width 125 ns
23 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. data formulas timer a input (gating input in timer mode) 8 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) limits min. max. symbol parameter unit t c(ta) tai in input cycle time t w(tah) tai in input high-level pulse width t w ( tal ) tai in input low-level pulse width ns ns ns 8 5 10 9 2 ? f(f 2 ) timer a input (external trigger input in one-shot pulse mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time ns timer b input (in pulse period measurement mode or pulse width measurement mode) limits min. max. symbol parameter unit ns ns ns t c(tb) tbi in input cycle time t w(tbh) tbi in input high-level pulse width t w(tbl) tbi in input low-level pulse width 8 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 4 10 9 2 ? f(f 2 ) note. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37735mhbxxxfp. 5
24 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) fig. 14 measuring circuit for each pin 50 pf cs 0 C cs 4 rsmp a 16 , a 17 a 0 /d 0 C a 15 /d 15 wel weh ale hlda p 4 p 5 p 6 p 7 p 8 1 rde limits min. max. t d(weCp4q) port p4 data output delay time 80 ns t d(weCp5q) port p5 data output delay time 80 ns t d(weCp6q) port p6 data output delay time 80 ns t d(weCp7q) port p7 data output delay time 80 ns t d(weCp8q) port p8 data output delay time 80 ns unit symbol parameter test conditions fig. 14 note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. microprocessor mode
25 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time 1 output delay time ____ hlda output delay time limits wait mode min. max. microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note 1)) symbol parameter test conditions t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( 1 Crsmp) t d(weC 1 ) t d(rdeC 1 ) t d( 1 Chlda) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 5 18 50 12 87 4 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 48 128 10 0 0 fig. 14 (note 2)
26 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz (max.), unless otherwise noted (note1)) 45 5 18 symbol parameter unit 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) ns ns no wait wait 1 wait 0 t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( 1 Crsmp) t d(weC 1 ) t d(rdeC 1 ) ns 4 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2? f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 ? f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) ns ns 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) ns ns ns ns ns ns 0 0 chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time 1 output delay time C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 32 C 32 C 30 C28 C 33 notes 1. this applies when the main clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37735mhbxxxfp. limits wait mode min. max.
27 mitsubishi micr ocomputers M37735S4BFP 16-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. t w(h) t d(weCp4q) t d(weCp5q) t d(weCp6q) t d(weCp7q) t d(weCp8q) rde, wel, weh x in port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input t su(p4dCrde) t su(p5dCrde) t su(p6dCrde) t su(p7dCrde) t su(p8dCrde) t r t f t w(l) t c t h(rdeCp4d) t h(rdeCp5d) t h(rdeCp6d) t h(rdeCp7d) t h(rdeCp8d) timing diagram
28 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event count mode t c(tb) t w(tbh) t w(tbl) tbi in input t su(taj in ?aj out ) t su(taj in ?aj out ) t su(taj out ?aj in ) t su(taj out ?aj in ) taj in input taj out input in event counter mode (when two-phase pulse input is selected) t c(ta)
29 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(knl) t d(c?) t su(d?) t h(c?) t w(inh) ad trg input clk i txd i rxd i inti input kli input t h(c?)
30 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. microprocessor mode (when wait bit = 1) (when wait bit = 0) (when wait bit = 1 or 0 in common) test conditions ? v cc = 5 v 10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 rdy input 1 rdy input 1 hold input hlda output t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) t su(holdC 1 ) t d( 1 Chlda) t h( 1 Chold) t d( 1 Chlda) wel weh rde wel weh rde
31 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. t w(we) t h(weCdq) t w(l) t w(h) t f t r t c microprocessor mode (no wait : when wait bit = 1) x in 1 cs 0 C cs 4 an ale am/dm t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) address t d(anCwe) t d(anCrde) t h(rdeCan) t w(ale) t d(aleCwe) address address t su(aCale) t h(aleCa) t d(aCwe) t d(aCrde) t d(aleCrde) t pxz(rdeCdz) t pzx(rdeCdz) address data address address wel, weh t h(weCan) t d(weCdq) dm in rde rsmp test condition ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) data t d(rdeC 1 ) t d(weC 1 ) t d(weC 1 ) t d(rdeC 1 )
32 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. t w(ale) t d(anCwe) t c am/dm address t d(csCrde) t w(rde) t d(rde- 1 ) t w(l) t w(h) t f t r microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection bit = 1.) x in 1 address cs 0 C cs 4 an ale wel, weh dm in rde rsmp t d(weC 1 ) t d(rdeC 1 ) t d(csCwe) t d(aleCwe) t h(rdeCan) t su(aCale) t h(aleCa) t d(aCwe) t d(weCdq) t w(we) t d(aCrde) t pxz(rdeCdz) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) test condition ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v address data address t h(weCcs) data t d(weC 1 ) t h(we-an) t d(aleCrde) t d(anCrde) t h(weCdq) address address
33 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. t h(aleCa) t d(aleCwe) t d(weCdq) t w(l) t w(h) t f t c t r microprocessor mode (wait 0 : the external memory are is accessed when wait bit = 0 and wait selection bit = 0.) x in 1 address address address address data cs 0 C cs 4 an ale am/dm wel , weh dm in rde rsmp t d(csCwe) t h(weCcs) t d(csCrde) t d(anCwe) t w(ale) t h(weCan) t d(anCrde) t h(rdeCan) t su(aCale) t h(weCdq) t d(aleCrde) t d(aCwe) t w(we) t d(aCrde) t pxz(rdeCdz) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t w(rde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) address data address test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t d(weC 1 ) t d(rdeC 1 ) t d(rdeC 1 ) t d(weC 1 )
34 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. package outline
35 mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. memo
? 1996 mitsubishi electric corp. h-lf426-a ki-9606 printed in japan (rod) new publication, effective jun. 1996. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers M37735S4BFP 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change.

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